Virtual metrology for 3D vertical stacking processes in semiconductor manufacturing

Current 2D planar NAND has its limitation for expanding capacity due to the performance and reliability intrinsic characterization will be impacted as device scaling below the 20nm technology node. Such as write bits error, data retention and read disturb, etc. Continued scaling increases the effect of cell-to-cell interference, which widens the program state width. 3D vertical stacking memory cells provide an innovative solution to boost the data-storage capacity of a chip without increasing its physical footprint. [1-2] From study of G.Y.Lee [3], traditional ex-situ furnace processes are no longer to serve 3D stacking device with over 32 pairs of oxide/nitride (ON) or oxide/doped polysilicon (OP) multilayer stacking NAND flash structure, it requires switching chambers for depositing each layer. They proposed to use in-situ, single-wafer sequence for depositing all layers in one chamber without breaking vacuum, and further suggest single wafer Plasma-Enhanced-Chemical-Vapor-Deposition (PECVD) process is the most feasible solution for this application. However, the thickness and uniformity in the complexity of ON or OP in-situ multilayer stacking processes are hard to monitor under in-line or off-line conditions. P. Kang [4-5] and S.A. Lynn [6] found the VM model can be built up by implementing the linear regression, support vector regression and multiple linear regressions for process improvement.