Dual High-k Gate Dielectric Technology Using Selective AlOx Etch (SAE) Process with Nitrogen and Fluorine Incorporation

We propose a novel V th , control method for HfSiON (or HfO 2 ) with poly-Si and metal inserted poly-Si stacks (MIPS) gates. By using a selective AlO x etch (SAE) process, we successfully integrate dual high-k gate oxide scheme; HfSiO/poly-Si stack for nMOS and HfSiO/AlO x /poly-Si stack for pMOS. Therefore, symmetrical V th values of 0.43V(nMOS)/-0.44V (pMOS) have been obtained in poly-Si gate. For MIPS gate, we perform the SAE process with impurity incorporation at the channel region, such as N 2 for nMOS and F for pMOS. Consequently, nMOS V th of 0.35V and pMOS V th of -0.45V are obtained without counter channel doping. Moreover, we find out that impurity incorporation at the channel also improves mobility and reliability characteristics. Finally, by using the SAE process with impurity incorporation, maximum operating voltages above 1.0V are obtained by an extrapolated 10 years lifetime