An approach to a high throughput matricial packet switch

A fully-hardware-based packet switch design is presented. The main features of its architecture are the nonblocking and noncontention basis of its implementation, which provides a high throughput capability and a low (and limited for all traffic situations) internal time delay. The approach used for this system assumes the development of several custom ICs which perform simple packet processing algorithms, embedded in hardware, and also takes advantage of the fast static memories now on the market. This fast switching system functions in a highly parallel processing way, and is well suited to support voice and data integration. >