FinFET Process and Integration Technology for High Performance LSI in 22 nm node and beyond

This paper discusses the key FinFET process and integration technologies to achieve high performance LSI. Firstly, side wall pattern transfer technique is introduced to realize an aggressively scaled down FinFET with 10 nm Fin width (W fin ) and 15 nm gate length (L g ). Next, dopant segregation (DS) Schottky technique is demonstrated to enhance the FinFET performance. Drive current of 960 muA/mum for DS Schottky nFinFET with L g = 15 nm at I off = 100 nA/mum and V d = 1.0 V is achieved. And then, FinFET SRAM is fabricated and studied in the view of static noise margin (SNM). SNM of 122 mV is obtained in the cell with W fin = 15 nm and L g = 20 nm at V d = 0.6 V. Also, fin height tuning technique is proposed so that SRAM operation can be optimized without area penalty. Finally, integration scheme of planar FET and FinFET is developed and verified to open up the possibility of the future SoC.