64 Kbit CMVP FeRAM macro with reliable retention/imprint characteristics

Packaged CMVP FeRAM chip reliability is evaluated for the first time. A 64 Kbit CMVP FeRAM macro is integrated with 0.35 /spl mu/m 3-level metallization CMOS logic devices. The ferroelectric properties of the PZT capacitor formed below 430/spl deg/C are not degraded even after plasma-SiON passivation. This is due to hydrogen barrier effect of TiN, and the high process damage immunity of the MOCVD PZT film. No failed bits are observed after a 240-hour retention/imprint period at temperatures between 25/spl deg/C and 150/spl deg/C with write/read voltages between 2.7 V and 5.5 V.