A Highly Linear and Flexible FPGA-Based Time-to-Digital Converter.

Time-to-Digital Converters (TDCs) are major components for the measurements of time intervals. Recent developments in Field-Programmable Gate Array (FPGA) have enabled the opportunity to implement high-performance TDCs, which were only possible using dedicated hardware. In order to eliminate empty histogram bins and achieve a higher level of linearity, FPGA-based TDCs typically apply compensation methods either using multiple delay lines consuming more resources or post-processing, leading to a permanent loss of temporal information. We propose a novel TDC with a single delay line and without compensation to realize a highly linear TDC by encoding the states of the delay lines instead of the thermometer code used in the conventional TDCs. Experimental results show that the empty histogram bins are reduced to less than 0.1% at the time resolution of 5.00ps, and have not been observed in the selected time resolutions of 10.04ps, 21.65ps, 43.87ps, 64.11ps, and 87.73ps. Our states-based approach achieves an improved Differential Non-Linearity (DNL) of [-1.00, -1.53] for 5.00ps, [-0.44,0.49] for 10.04ps, and [-0.07, 0.05] for 87.73ps. We have achieved a TDC with higher raw linearity, reduced empty bins, and a simpler structure compared with the previous FPGA-based TDC.