A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry
1995
A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates has been developed. To provide good testability, reliability, and stability, on-chip test circuitry, a memory-cell test technique, a highly stable current source, and a soft-error-immune memory cell are proposed.
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