Gate-All-Around technology: taking advantage of ballistic transport ?

This work presents an experimental study in order to evaluate the quality of transport in state-of-the-art Gate-All-Around devices. 25nm×20nm×10nm (LxWxT Si ) silicon channel devices with metal/high-k gate all-round stack were characterized electrically in terms of mobility and limiting velocity in order to evaluate the possible occurrence of ballisticity. Conclusions are finally presented in the scope of elementary circuit perspectives.