High performance of planar double gate MOSFETs with thin backgate dielectrics

Planar double gate CMOS devices with thin silicon channels and electrically separate polysilicon top and bottom gates are fabricated. NFETs with L/sub design/=175 nm and 1.3 mA//spl mu/m and PFETs with L/sub design/=125 nm and 400 /spl mu/A//spl mu/m are achieved at V/sub dd/=1.2 V. To our knowledge, this is the largest current yet achieved in double gate NMOS devices. Electrical results show a high quality backgate dielectric, improvement of SCE using the backgate, and the importance of reducing external resistance in short channel devices.