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Neo-chips suitable for stacking in 3D multi-layer electronic modules are formed by embedding (encapsulating ) IC chips in epoxy material which provides sufficient layer rigidity after curing. The encapsulated chips are formed by placing separate IC chips, usually "known good" die, in a neo-wafer, which is subjected to certain process steps, and then diced to form neo-chips. The following benefits are obtained: (1) The starting IC chips (die) intended for stacking may have different sizes, and serve different electronic purposes. After they are encapsulated in same-size neo-chips, they can be efficiently stacked using well-developed processing steps; (2) The individual chips for stacking can be purchased as "known good" die. This means than an essentially unlimited choice of die is available to the stacking entity, and that the die are pretested when they are ready for stacking; (3) A given layer can contain a plurality of individual die; and (4) The die encapsulating material is dielectric, so that no special steps are required to prepare the access plane of the stack for metalization. Heretofore, this preparation of the access plane has required either the etch-back plus passivation process, or the passivation plus trench-formation process.