Effects of TSVs (through-silicon vias) on thermal performances of 3D IC integration system-in-package (SiP)

Abstract Thermal performances of 3D IC integration system-in-package (SiP) with TSV (through silicon via) interposer/chip are investigated based on heat-transfer and CFD (computational fluid dynamic) analyses. Emphases are placed on the determination of (1) the equivalent thermal conductivity of interposers/chips with various copper-filled, aluminum-filled, and polymer w/o filler filled TSV diameters, pitches, and aspect ratios, (2) the junction temperature and thermal resistance of 3D IC SiP with various TSV interposers, (3) the junction temperature and thermal resistance of 3D stacking of up to 8 TSV memory chips, and (4) the effect of thickness of the TSV chip on its hot spot temperature. Useful design charts and guidelines are provided for engineering practice convenient.