Investigation of different methods for isolation in through silicon via for 3D integration

3D integration is now a realistic, mainstream solution to tackle the issue of device scaling and achieve decreased RC delay times and reduced power consumption, by using through-silicon-vias (TSV). In this architecture, a via liner performs multiple functions as an insulator, a Cu diffusion barrier and an adhesion promoter. The dielectric layer is the key element in fulfilling the electrical requirements for TSV when a high aspect ratio of more than 5:1 is used. This paper presents a new methodology for creating a dielectric liner by using a dual plasma-enhanced/high-pressure chemical vapour deposition (PE/HPCVD) layer of SiO"2 to produce a better 3D integration solution than today's commonly used SiO"2 deposition process.