Firmware Development for the first level trigger of ATLAS LAr Calorimeter

The LHC Run3, which is scheduled to be 2021-2023, is expected to have two times higher instantaneous luminosity than Run2. This leads a large drop on the acquisition efficiency of W / Z boson events at the first level trigger of the ATLAS Liquid Argon calorimeter. In order to tolerate an increasing instantaneous luminosity, the trigger readout is upgraded to read 10 times finer granularity than the current trigger readout. This leads to the improvement of a separation power between EM objects (electron, photon) and hadronic jet. A FPGA firmware which manages huge data (RX : 5.12 Gbps×96, TX : 11.2 Gbps×96) with a fixed latency is in the backend electronics of the upgraded trigger readout. We implemented a multi-stage impulse response filter with high-speed links to convert digitized signals into deposited transverse energy at a correct bunch crossing of LHC beams. The designed firmware satisfies the requirements of the fixed latency, FPGA resources and the maximum operation frequency. We confirmed the stability of the firmware on a hardware.