A 14-BIT 1.2GS/S TIME-INTERLEAVED PIPELINE ADC WITH CALIBRATION

A 14-bit 1.2GS/s ADC fabricated with 0.18μm CMOS process is presented in this paper, Which is realized by interleaving four 14bit 300 MS/s pipelined sub-ADC (PADC) on a single chip. An optimized buffer is designed to improve the sampling linearity and bandwidth of TI ADC. A dedicated foreground calibration method is used to correct the nonlinearity of sub-ADC and input buffer with little extra hardware cost for analog circuit. Background calibration techniques are used to eliminate the inter-channel mismatches between time-interleaved sub-ADCs. Measure results show that an SFDR of 79.8 dB and an SNDR of 65.8 dB can be achieved after calibration for a 55 MHz input. The chip consumes 1.26W under 1.8V/3.3V supply.