Techniques for reduced power and increased speed in dynamic and ratio logic circuits

This paper describes three techniques for increasing the usefulness of dynamic and ratio logic circuits. The first allows the power of pre-discharged ratio logic circuits to be significantly reduced. The second approach improves the speed of a dynamic and ratio logic circuit by partitioning the common heavily loaded node. Finally, a circuit approach is disclosed that implements a low threshold NFET to improve the speed of a dynamic circuit. Each technique demonstrates the use of a heavily loaded dynamic or ratioed logic NOR gate.