Extending immersion lithography to the 32-nm node

C045 node (65nm half pitch) technology processes are driving the development of immersion lithography techniques and infrastructures and C032 node (45nm half pitch) is following in its tracks. As semiconductor development enters the arena of low leakage, high-performance devices using immersion lithography, the 45nm hp technology adds more pressure of decreasing pitches and feature sizes using the most cost effective method available. The Crolles2 Alliance is in the first phases of the push for very low k1 193nm lithography for our technology development. Many resolution enhancement techniques are being explored to fill the low k1 realm; including implementation of these techniques and more aggressive integrations to support the device parameters. However, the early development of 45nm hp node along with the need for better focus and dose control algorithms, imaging of pitches to allow for the packing density will present significant challenges to photolithography even when considering super hyper-NA immersion lithography. Reflectivity variations, thin film interference through the complex film stacks, and increased sensitivity to feature size is posing a challenge for maintaining good and consistent features. This paper discusses an analysis and early results covering the beginning development of 45nm hp with >1NA immersion lithography. Specifically, parameters such as illumination and enhancement techniques, processing capability, application of OPC at a very low k1, process integration, mask effects, and defectivity as discussed.