Old Web
English
Sign In
Acemap
>
Paper
>
COGRE: A Novel Compact Logic Cell Architecture for Area Reduction
COGRE: A Novel Compact Logic Cell Architecture for Area Reduction
2010
Okamoto Yasuhiro
Ichinomiya Yoshihiro
Amagasaki Motoki
Iida Masahiro
Sueyoshi Toshinori
Keywords:
Logic synthesis
Computer architecture
Diode–transistor logic
Logic gate
Logic family
Programmable logic device
Logic optimization
Electronic engineering
Resistor–transistor logic
AND-OR-Invert
Mathematics
Correction
Source
Cite
Save
Machine Reading By IdeaReader
0
References
0
Citations
NaN
KQI
[]