Low Temperature Fusion Wafer Bonding for Wafer-Level 3D Integration Applications

A low temperature fusion bonding process based on plasma activation of surfaces prior bonding was developed. The results obtained during process characterization could not be explained by the known bonding mechanism for silicon fusion bonding (reported in literature). The investigations lead to development of a new model, which will be introduced. The process condition is compatible with the high cleanliness levels required by CMOS technology and can be used for various application scenarios involving Through-Silicon Vias (TSV) technology.