9.6 A 1.3mW 0.6V WBAN-compatible sub-sampling PSK receiver in 65nm CMOS

The release of the IEEE802.15.6 standard has led to increased interest in low-power technologies for wireless body-area-networks (WBAN). The power dissipation, supply voltage, and IC area are some of the most important criteria for successful WBAN implementations. Analog-intensive heterodyne receivers (RX) have been previously demonstrated, consuming 4 to 5mW of power from a 1-to-1.2V supply while occupying large silicon area, due to the presence of area-intensive analog building blocks such as low-pass filters at the IF [1,2]. Digital-intensive RX architectures can potentially result in sub-1V operation with significant reductions in power consumption and area, but require system and circuit-level innovations to achieve desired sensitivity and linearity. This paper presents a mostly-digital 2.4GHz RX architecture that uses a sub-sampling technique with digital IF/baseband signal processing to enable low-power (1.3mW) and low-voltage (0.6V) operation, resulting in ~3x reduction in power consumption. Early analog-to-digital conversion leads to the IC occupying only 0.35mm 2 of active silicon area. While the IC focuses on WBAN demodulation, the presented techniques are applicable to other low-power standards as well.