Impact of physical defects on the electrical working of embedded DRAM with 0.35 /spl mu/m design rules

The impact of physical defects generated by the process has been studied on embedded Dynamic Random Access Memory (DRAM) chips, with 0.35 /spl mu/m design rules. In-line automatic inspections have been performed at several steps of the process, on deposited or etched layers, with a darkfield, pixel-to-pixel comparison system. The defects detected have been systematically reviewed and characterized with an optical microscope or a scanning electron microscope (SEM) with X-ray analysis. Electrical failures have been traced back to their origin. Analysis of the correlation between physical and electrical defects has highlighted the main causes of yield loss. Moreover, the physical defects have been subdivided into classes associated with different types of failure, thus enabling the yield to be predicted during the process.