2T-SONOS Cell Using Novel Process Integration on HV-CMOS Platform for Versatile Application

We report on a low cost, secure 2T-SONOS embedded nonvolatile memory (eNVM) using a novel contamination free process integration. The proposed 2T-SONOS cell utilizes reverse read method resulting in wide threshold voltage ( $\boldsymbol{V_{T}}$ ) window read margin. Using an eNVM on a 90 nm high voltage CMOS process, touch screen controller (TSC) embedded display driver IC application as well as wide input range TSC is possible. Unit cell shows 6 volt program and erase $\boldsymbol{V_{T}}$ window. However, 32 kB IP shows lower $\boldsymbol{V_{T}}$ window of 2 V due to cell $\boldsymbol{V_{T}}$ distribution, source side resistance and program disturb effect during programming. In case of programmed cells, both fresh and 1 k program/erase (P/E) cycled cells show abrupt initial $\boldsymbol{V_{T}}$ shift of 0.5 V after 48 hours of 120 °C bake test. However, erase $\boldsymbol{V_{T}}$ shift happened only at 1 k P/E cycled cell. Regardless of cycling and program/erase states, after 48 hours of bake, $\boldsymbol{V_{T}}$ shift was saturated. Thanks to the charge trap layer contamination suppressing novel process integration and optimized charge distribution, 120 °C data retention lifetime of over 10 years after 1k P/E cycling is obtained without using any special band gap engineered materials.