The development of a low-stress polysilicon process compatible with standard device processing

When surface micromachined devices are combined with on-chip circuitry, any high-temperature processing must be avoided to minimize the effect on active device characteristics. High-temperature stress annealing cannot be applied to these structures. This work studies the effects of deposition parameters and subsequent processing on the mechanical properties of the polysilicon film in the development of a low-strain polysilicon process, without resorting to high-temperature annealing. The films are deposited as a semi-amorphous film and then annealed, in situ at 600/spl deg/C for 1 h, to ensure the desired mechanical characteristics for both doped and undoped samples. This low temperature anneal changes the strain levels in undoped films from -250 to +1100 /spl mu//spl epsi/. The best results have been obtained for an 850/spl deg/C anneal for 30 min which is used to activate the dopant (both phosphorus and boron). No further stress annealing was used, and 850/spl deg/C does not present problems in terms of thermal budget for the electrical devices. It is shown that these mechanical characteristics are achieved by forming the grain boundaries during subsequent low temperature annealing, and not during deposition. TEM (transmission electron microscopy) studies have been used to investigate the link between the structure and mechanical strain. This has shown that it is the formation of the grain boundary rather than the grain size which has a significant effect on strain levels, contrary to reports in the literature. Using the above-mentioned deposition process, a series of experiments have been performed to establish the flexibility in subsequent processing available to the designer. Therefore, by careful consideration of the processing, a low-temperature polysilicon process, which can be used to fabricate thin micromachined structures, has been developed.