A sea-of-gates-based, 10 MIPS 16-bit RISC processor testbed for failsafe applications

A sea-of-gates-based, 16-bit RISC processor testbed with a maximum performance of 10 MIPS at a 20 MHz clock rate is described. Starting from a small core requiring only 3000 gates, features can be added in a flexible manner to obtain various system architectures suited for failsafe applications. The core has a load-store Harvard architecture with 24-bit instructions, a 16-bit data path, and a two-stage pipeline. The data path contains sixteen 16-bit general purpose registers and a high-speed 16-bit carry-select adder. The core version has been fabricated on a 1.2 mm GATE FOREST master. An experimental version with control flow checking, boundary scan capability with integrated pad-test and 100% stuck-fault coverage is in fabrication. Software support includes high-level and RT-level simulators, assembler and PASCAL-compiler. >