8Å T inv gate-first dual channel technology achieving low-V t high performance CMOS

We report low V t (V t,Lg=1µm =±0.26V) high performance CMOS devices with ultra-scaled T inv down to T inv ∼8A using a gate-first dual Si/SiGe channel low-complexity integration approach. Compared to a dual dielectric cap gate-first integration scheme, the devices fabricated with the novel scheme show for the same high-k/metal gate stack (1) 3A reduction in nMOS and pMOS T inv (2) 220mV lower long channel pMOS V t (3) 21%/12% pMOS/nMOS drive current increase at I off =100nA/µm and (4) 50% improvement in long channel pMOS Vt variability. For a fixed T inv of 12A, a 4 times higher hole mobility and 350mV increase in NBTI 10years lifetime operating voltage are obtained.