S-band GaN LNA with OIP3 >50dBm using parallel independently biased gates

GaN devices have comparable noise figures to GaAs devices, while being able to withstand very high input drives. This paper presents the design of GaN low noise amplifier (LNA) from 2–4 GHz (S-Band) with Pout ∼ 37dBm, Noise figure (NF) from 1.8–3.5dB, and output referred third order intercept point (OIP3) from 48–54dBm. The linearity performance can be increased by splitting the output stage, which has a gate periphery of 2.5mm, into two parts of 1.25mm each and optimizing their bias. Biasing the two FETs differently leads to phase cancellation of IMD3 components and improvement in OIP3 performance. The experimental results show up to 9.5dBm of improvement in the OIP3 when one gate is biased in Class AB and the other is in deep Class AB mode. Linearity FOM (OIP3/Pdc) is also improved, reaching up to 14 at higher Pouts.