Novel patterning schemes and technologies for the sub 5nm era

Multipatterning has enabled continued scaling of chip technology at the 28nm logic node and beyond see Fig. 1. Self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) as well as Litho-Etch/Litho-Etch iterations are widely used in the semiconductor industry to reach sub 193 immersion lithography resolutions for critical layers such as FIN, Gate and Metal lines. Multipatterning requires the use of multiple masks, which is costly and increases process complexity as well as edge placement error variation mostly driven by overlay. In our presentation, we will propose and demonstrate novel patterning concepts, which can curb some of these downsides and usher in the next technological advancements required for further scaling. We will also survey the progress and maturity of EUV patterning in contrast to multipatterning options.