Low-power high-performance arithmetic circuits and architectures

A new class of dynamic differential logic families, swing limited logic (SLL), is proposed for low-power high-performance applications. Two implementations of SLL, short-circuit current logic (SC/sup 2/L) and clock-pulse controlled logic (CPCL), are designed. Low power is achieved by aggressively reducing logic swing. Using a 0.35-/spl mu/m CMOS technology and a nominal supply voltage of 3.3 V, an SC/sup 2/L 8-bit carry ripple adder (CRA) is implemented. It offers an order of magnitude less energy-delay product than several other logic families. Furthermore, two multipliers are constructed to demonstrate how SLL can be used in large circuit applications.