The design of a 14-bit 400kSPS non-binary pipeline cyclic ADC

This paper presents a 14-bit, 400ksps pipeline cyclic analog-to-digital converter (ADC) in 90nm CMOS technology. Each stage is a non-binary cyclic ADC based on s-expansion and the proposed ADC is designed in 3-stage pipeline structure. 16-bit non-binary output code of 3-stage is selected as 4-4-8 bits according to the considerations of total power consumption and conversion speed of the ADC. We also proposed a radix-value estimation technique for multi-stage non-binary ADC to realize the high linearity of this pipeline cyclic ADC. The SPICE simulation results demonstrate the feasibility and validity of the proposed ADC architecture and radix-value estimation algorithm. Simulated ENOB=14.25-bit is achieved while Fs = 400kSPS. The power consumption of proposed ADC is 10.59mW while the supply voltage is 3.0V.