Spin on glass (SOG) etch-back planarization process: an industrial solution for 0.5-um CMOS TLM technology

A SOG/etch-back process has been developed in order to be compatible with a 0.5 micrometers triple level metal technology with plugged vias. Four SOG are compared in terms of planarization level after coating but also after etch-back. The etching process is studied in order to reach the low selectivities required to compensate the microloading effects of patterned wafers. The compromise between high planarization level and low surface roughness is obtained by adjusting selectivity and etching time. Planarization level and complete SOG consumption, required to avoid vias poisoning, can be controlled by measuring TEOS1 consumption after etch-back. Vias and metal yield are measured on different topographies. Results illustrate the planarization efficiency.