Development of high-performance ultra large scale 3D processor with high reliability packaging design

3D-LSI packaging technology with trough silicon via (TSV) is useful for high density and shortened wiring to achieve low power consumption and wide bandwidth for high performance processor. [1] As expected in processor functions, making logic circuit areas larger is required as the scale-up of calculation processing capability, following the trend of many recent core or graphics processing units. By developing 3D-LSI packaging technology compatible with ultra large chips for high-performance processor, and overcoming the issue of yield and reliability, we have achieved a 3D stacked design technology and micro-bump materials of high-yield at product level on a stacked logic processor with almost 700-mm square as the full reticle shot size. In this study, we present the 3D packaging design method to reduce the micro bump stress that originated the underfill material to achieve large size 3D LSI for logic circuit. It was found that the combination of chip organization with a lower stiffness in the stacked structural stability and lower CTE underfill material influenced the vital structure reliability for large chips.