A 3 GHz, 32 dB CMOS limiting amplifier for SONET OC-48 receivers

An optical receiver front-end for SONET OC-48 (2.5 Gb/s) is shown. The limiting amplifier (LA) receives a small-non-return to zero (NRZ) voltage signal (e.g., 8 mV/sub pp/) from the transimpedance amplifier (TIA) and amplifies it to a level (e.g. 250 mV/sub pp/) sufficient for the reliable operation of the clock and data recovery circuit. The noise contribution of the LA must be small compared to that of the TIA so that the overall bit error rate and sensitivity are not affected adversely. Currently, commercial 2.5 Gb/s SONET systems are composed of several discrete chips implemented in GaAs and more recently silicon bipolar technology. The future trend, however, is to integrate most of the front-end together with the digital framer on a single CMOS chip. Furthermore, the integration of multiple 2.5 Gb/s channels on a single CMOS chip is desirable for wavelength division multiplexing (WDM) application. CMOS amplifiers for optical receivers and related applications with bandwidths up to 2.1 GHz are recently reported. This CMOS limiting amplifier with improved bandwidth (3 GHz) and noise figure (16 dB) is suitable for 2.5 Gb/s SONET receivers. Power dissipation is 53 mW and the chip is fabricated in a standard 2.5 V, 0.25 /spl mu/m CMOS technology. This result is achieved with: (i) Inverse scaling to increase gain-bandwidth and reduce power dissipation while keeping noise and offset voltage low and (ii) active inductors to increase gain-bandwidth and improve gain stability. The active area of the amplifier is 0.03 mm/sup 2/, less than 10% that of a comparable design with spiral inductors.