New Challenges of Design for Reliability in Advanced Technology Node (Invited)

With the dimension of transistor scaling down to 5nm, design for reliability attracts more and more attentions in digital and analog circuit. Self-heating effects must be taken into account due to the introduction of FinFET structure, which will be more serious with thinner and higher Fin shape optimization and future GAA nanowire. Self-heating related qualification is also critical, since it may impact the HCI, EM and TDDB. Moreover, BTI and HCI degradation show new feature as stochastic nano-reliability in small area transistors, since single trap induced degradation becomes more obvious. Aging induced variation has also been shaving away the design margins, especially in SRAM, this effect will be discussed in detail in this paper from transistor to product.