Sub-threshold Drain Current model of Double Gate RingFET (DG-RingFET) Architecture: An Analog and Linearity Performance Investigation for RFIC Design

ABSTRACTIn the present work, impact of Double Gate RingFET (DG-RingFET) has been investigated for better gate control and suppressed Short Channel Effects (SCEs) using ATLAS 3D device simulator. The analog performance metrics explored in this paper are drain current (Ids − Vgs), trans-conductance (gm), device efficiency (gm/Ids), and early voltage (Vea). In addition to this linearity behaviour of DG-RingFET has been investigated in terms of third-order voltage intercept point (VIP3), third-order current intercept point (IIP3), third-order inter modulation distortion (IMD3) and results are also compared with the single gate architecture. The two-dimensional analytical model for DG-RingFET architecture has also been developed in this paper using parabolic approach. Moreover, the impact of technology variations like drain radii and position of drain, i.e. inside or outside the channel ring on the performance of DG-RingFET architecture has also been assessed.