RLC signal integrity analysis of high-speed global interconnects [CMOS]

Inductive and capacitive coupling effects for high-speed global interconnects are studied via simulation. The impact of inductive coupling on delay and noise is found to be comparable to capacitive effects in high-speed buses. The results indicate that current-return paths are not strictly bounded by wide VDD/GND lines, so that inductive coupling is only partially eliminated by using shield wires. Shielding strategies for noise- and delay-sensitive nets is proposed, considering worst-case switching patterns.