Surface-tensile-stress induced polishing-voids in cross-point phase-change-memory cells: corrosion mechanism and solution

In the fabrication of cross-point phase-change-memory-cells through atomic-layer-deposition of Ge-doped SbTe (Ge-ST) film followed by chemical-mechanical-polarization (CMP), a remarkable surface tensile stress was generated, originating from the surface stress induced by the pad down force and the surface structure tensile stress in a confined memory-cell structure. It was maximized at the position of the Si3N4-film spacer where the curvature becomes zero. The maximized surface tensile stress produced polishing induced voids via the generation mechanism of the stress corrosion cracking. The generation frequency and nanoscale size of the polishing induced voids rapidly increased at the maximum surface tensile stress during CMP. Then, they slightly decreased and saturated when the surface tensile stress reduced during further CMP. A design of a spacer using a SiO2-film spacer rather a Si3N4-film spacer could prevent the generation of the polishing induced voids, confirming that the generation mechanism of the polishing induced voids is associated with the stress corrosion cracking.