Reduction of RTA-driven intra-die variation via model-based layout optimization

Unique hybrid approach employing both model-based layout optimization and process improvement was successfully developed for reducing rapid thermal anneal (RTA) driven intra die variations. It has been applied to multiple bulk and SOI designs. The model developed herein enables fast estimation of broad-band reflectance of a random layout in 65 nm, 45 nm, and 32 nm nodes and guides reflectance leveling in the post-design phase. This approach significantly reduces RTA-driven variations showing 30% reduction in intra die ring oscillator range in high-performance products.