Low-Latency and Low- Area Overhead Based Performance Modeling of Network on Chip Architecture for FPGA Based Computing System

This paper contributes in the enhancement of NoC architecture with respect to area & Latency. A switch/Router size 4*4 is targeted. The input/output module with efficient buffer to store the data packet while waiting for the scheduling is optimized at architecture level with respect to area & latency and observed that the design is operating at 305.573 MHz, with latency 2 per clock cycle and result are compare with other publications.