Bipolar technology for 0.5-micron-wide base transistor with an ECL gate delay of 21.5 picoseconds

This paper presents a high speed Si bipolar transistor using polysilicon sidewall base-electrode transistor (POSET) technology developed from self-aligned silicon bipolar transistor technology. We reduced the parasitic capacitance between the base and the collector to a minimum to maximize the transistor's speed. Other techniques were used to make a practical device with a gate delay time of 21.5 ps/gate at a switching current of 0.32 mA. This is faster than any commercial bipolar transistor at a switching current about one third. >