Linear Current-to-Time Converter

In this work, a new current-to-time converter (CDC) based on current-starved inverter is proposed. The time delay of the output pulse edges is linearly proportional to a control current. The benefits of the proposed topology are simple circuit topology, linear current-to-time characteristic with positive or negative slope for both rising and falling edges. The circuit is designed and tested using 0.35um CMOS process under 3V supply voltage. The linearity error is less than 2.1% in a range of 5nsec of time delays with a clock frequency of 50MHz.