Optimum transistor sizing of CMOS logic circuits using logical effort theory and evolutionary algorithms

Abstract Most existing methodologies use either Logical Effort (LE) theory or stand-alone optimization algorithms for automated transistor sizing of CMOS logic circuits. LE theory optimizes a logic circuit only with respect to speed while it completely ignores power and area. Whereas heuristic algorithms when used as a stand-alone approach for optimization lead to huge computational effort since there is no predefined technique to apply constraints on transistor sizes in order to limit the design space for target specifications. The problem has been resolved in this paper by utilizing delay sensitivity factor based on LE theory proposed by Alioto et. al. [1] for estimating the highest operating speed of a logic circuit and determining the upper bound on the size of transistors. Recently proposed heuristic algorithms viz. Interior Search Algorithm (ISA) [2] and Gravitational Search Algorithm (GSA) [3] have been utilized further to converge towards minimum power-delay-area product (PDAP). Simulation results for various test circuits indicate upto 35.1% and 63.8 % improvement in power-delay product (PDP) and PDAP respectively in 130 nm/1.2 V TSMC CMOS technology. PVT analysis and Monte Carlo simulations have been used to further validate the effectiveness of the proposed methodology.