High mobility CMOS: First demonstration of planar GeOI p-FETs with SOI n-FETs

Abstract We report for the first time the fabrication and the electrical operation of a Ge and Si based CMOS planar scheme with GeOI p FETs and SOI n FETs, taking advantage of the best mobility configuration for holes (Ge) and electrons (Si). The hybrid Ge/Si wafers have been obtained by the local Ge enrichment technique on SOI wafers. A sub 600 °C CMOS transistor process featuring High-K/Metal Gate and silico-germanidation was used to obtain functional high mobility CMOS transistors (down to L  = 160 nm). Excellent low-field mobility values for electrons in Si n FETs and holes in Ge p FETs were achieved (275 and 142 cm 2 /V/s resp.).