Chemical analysis of deposits formed on the reactor walls during silicon and metal gate etching processes

One major challenge in plasma etching processes for integrated circuit’s fabrication is to achieve wafer-to-wafer repeatability. This requires an excellent control of the plasma chamber wall conditions. For gate etching processes this is achieved by cleaning the interior surfaces of the plasma chamber with appropriate plasma chemistries after each wafer is etched. This strategy relies on the knowledge of the chemical composition of the layer coated on the reactor walls after the etching process. However, this is generally not the case and the chemical nature of this layer varies significantly with the etching conditions. In particular, the chemical nature of the coatings formed on the reactor walls during gate etching processes, which require up to seven successive etching steps in different plasma chemistries, has never been investigated in detail. In addition, the introduction of metals and high k in the gate stack can lead to types of coatings on the reactor walls. In the present article, we have used ...