An 8-Point IDCT computing resource implemented on a TriMedia/CPU64 reconfigurable functional unit

This paper presents the implementation of an 8-point Inverse Discrete Cosine Transform (IDCT) comput- ing resource on a TriMedia/CPU64 FPGA-based Reconfig- urable Functional Unit (RFU). TriMedia/CPU64 is a 64-bit 5 issue-slot VLIW processor launching a long instruction ev- ery clock cycle. The RFU consists mainly of an FPGA core, and is embedded into the TriMedia as any other hardwired functional unit, i.e., it receives instructions from the instruc- tion decoder, reads its input arguments from and writes the computed values back to the register file. To reduce the computational complexity of IDCT, we used a modified ver- sion of the Loeffler algorithm which requires 14 multipli- cations. Since each multiplicand is a 16-bit signed number represented in 2's complement notation, while each multi- plier is a positive constant of 15 bits or less, we employed a "multiplication-by-constant" scheme which was optimized against the multiplier. To increase the throughput of the IDCT computing resource, we propose a pipeline implemen- tation. When mapped on an ACEX EP1K100 FPGA-based RFU, our 8-point IDCT computing resource exhibits a la- tency of 16 TriMedia cycles, a recovery of 2 cycles, and oc- cupies 42% of the logic cells of the device.