Lithography-patterning-fidelity-aware electron-optical system design optimization

Low-energy electron beamlithography is a promising patterning solution for the 21 nm half-pitch node and beyond due to its high resolution, low substrate damage, and increased resist sensitivities. To ensure a successful electron-optical system (EOS) design, many factors such as focusing properties (FPs) and patterning fidelity (PF) have to be considered. In traditional EOSoptimization flow, FPs are typical performance indices selected when optimizing the EOS design parameters. In each numerical iteration, the EOS FP simulation results are compared with specified performance index values. The differences are reduced by adjusting the EOS design parameters until convergence. However, the performance indices related to FPs may have no direct relation to lithography PF, which is judged by the quality of the developed resist patterns. A new EOS design methodology which directly incorporates lithography PF metrics into the optimization flow is proposed. The EOS design parameters are first optimized while meeting the geometric constraints by using the traditional design flow to obtain acceptable FPs. In order to ensure lithography PF, writing patterns are selected and writing parameters are optimized. Then, constraints and cost functions related to PF are selected to further optimize the EOS design parameters to obtain acceptable PF. In each numerical iteration, the simulated lithography patterning results are compared against specified PF metric values. Their differences are reduced by adjusting the EOS design parameters until all constraints are met and PF cost functions are converged. The proposed method is applied to an EOS structure design for a 5 keV electron beamlithography system which includes a single-gate source and a focusing lens. Initial values of EOS design parameters and geometric constraints are selected based on previous studies. A drawn layout for a 22 nm isolated line pattern is used for verifying the lithography PF specifications based on the International Technology Roadmap of Semiconductors. The developed resist pattern after applying the proposed method clearly indicates that the PF is significantly improved from the value of corresponding critical dimension (CD) and the value of gate CD control.