Comparison of three monolithically integrated TIA topologies for 50 Gb/s OOK and PAM4

Parasitics such as wirebond inductances and bond pad capacitances that result from hybrid opto-electronic integration pose a challenge towards achieving data rates beyond 50 Gb/s. The effect of bond pad capacitance on the receiver transimpedance limit is shown, which demonstrates the significant advantage of monolithic versus hybrid integration. An analysis of three receiver topologies is presented. These all employ the same Cherry-Hooper voltage amplifier for the core electronics. A comparison across several design metrics of the three Transimpedance amplifier (TIA) variants is then provided. The TIAs are implemented monolithically in the IHP 250-nm SiGe BiCMOS EPIC process (fT = 190 GHz). Measurement results are then presented for 50 Gb/s OOK. PAM4 simulations are also shown.