Yield and reliability in flip chip underfill for optical modules

The increase in Flip Chip (FC) die size, standoff developments (gaps) and trends towards higher functionality pose continuous challenges for void free packaging in flip chip underfill processes. Current conditioning techniques prior underfill or molding, are typical surface treatments using gas plasma activation. The main goal of the plasma treatment is surface cleaning or modification to improve adhesion of the underfill or mold compound to the substrate and prevent delamination or voids in the polymer substrate / chip interface resulting in yield loss. This study examines the general failure modes associated with the FC underfill process and a comparison of the yield with and without the plasma activation for an optical module with large FC size of 20mm × 20mm. In order to better understand the surface treatment effects a comparison between different plasma excitation frequencies has been established. The findings have been transferred to an icPhotonics™ optical FC module. The module allows for aggregate full duplex data rate of better than 1.30 Tb/s with Bit Error Rate (BER) < 1E-12 into and out of a single ASIC die for distances up to 300m.