A Novel “hybrid” high-k/metal gate process for 28nm high performance CMOSFETs

A “hybrid” high-k/metal gate (HK/MG) integration scheme is proposed in this paper to accomplish HP (high performance) 28 nm CMOSFETs by integrating gate-first/gate-last (GF/GL) techniques for N/PFET, respectively. For NFET, remarkable mobility (95% of n + poly/SiON@1MV/cm) and low V TH (0.25 V) was achieved through optimized HfO 2 high-k, TiN metal and LaO x capping layer processes. For PFET, an extra 30% performance improvement and a low V TH (0.25V) were achieved by GL process as a result of strain boost and VFB roll-off alleviation [1].