Parallel morphological template matching design for efficient human detection application

In this paper, we present a VLSI design of human detection using Sum of Absolute Difference (SAD) based parallel morphological template matching method. Its research targets are to achieve small area consumption yet with fast computation. The architecture is designed to process original and its template images with resolution of 640×480 and 40×100 pixels respectively. Here, we propose two techniques, a rolling-index architecture for SAD computation and an optimized binary tree adder. For every calculation window, the difference between source and template is calculated in parallel processing. Hence, the SAD calculation computes 40×100 pixels per clock cycle. The proposed design is coded using Verilog HDL and implemented in Altera Cyclone II FPGA. The full processing time needs 307,200 clock cycles. Each image frame needs 6.144 ms and the frame speed reaches 162 frame-per-second (fps) for video application. This proposed design only consumes 16,689 logic elements, comprising 12,732 combinational functions and 4,460 dedicated logic registers.