Improving after-etch overlay performance using high-density in-device metrology in DRAM manufacturing

In advanced DRAM semiconductor manufacturing, there is a need to reduce the overlay fingerprints. Reducing on device fingerprints with very high spatial frequency remains one of the bottlenecks to achieve sub-2nm on device overlay. After-etch device overlay measurements using the YieldStar in-device metrology (IDM)[1] allow for previously unassessed and uncontrolled fingerprints to be corrected employing higher-order overlay corrections. This is because this technology allows dramatically increased overlay metrology sampling at affordable throughputs. This paper reports considerations for enabling dense after-etch overlay based corrections in a high volume manufacturing environment. Results will be shown on a front end critical layer of SK hynix that has been sampled with IDM with high density wafer sampling, over dozens of lots spanning several weeks.