Linearity Enhancement Method for a Wide-Band Digitally Controlled Oscillator

A linearity enhancement technique for a wide-band digitally controlled oscillator (DCO) is presented in this paper. By adding a calibration resistor array to improve frequency-tuning characteristics, the DCO shows a highly linearized frequency tuning curve without demanding much more power and silicon area. A prototype is designed and fabricated using a 55-nm CMOS process. The test chip has a measured frequency tuning range from 1.3 GHz to 2.5 GHz while occupying 225 × 180 µm2. The measured coarse bank tuning maximum DNL is 0.39 LSB and the maximum INL is 4.64 LSB which has been reduced to 43% of the conventional design's. The maximum power consumption is 15.8 mW from a 1.2 V supply voltage.